Low-Power 12-Gbps Multi-Standard SERDES PHY


CFP: #79 Round: 15
Unversity/Faculty: Ain Shams University Project Type: PRP Company: N/A
ITAC Fund: EGP 128,960 Start Date: 10/1/2014 End Date: 6/30/2015

Project Output:

The objective is to implement a multi-standard SERDES transceiver PHY IP that can operate up to 12 Gbps data rate. The IP design will focus on reducing the power consumption of the transceiver, setting an ambitious goal of 5 pJ/bit or lower and a random generated jitter of 1 ps or lower while meeting all the standards specifications with easy programmability.


Project KPIs:

  • Commercial Indicator :

    Partnership: Partnership with Mipex to continue other phases of the project

  • Technology Indicator :

    Conference Papers:

    • A 15.5-mW 20-GSps 4-bit charge-steering flash ADC
    • Current Steering Charge Pump with Low Current Mismatch and Variation
    • Low-power charge-steering phase interpolator

  • Job Creation:

    (1) Design Engineer at Mipex